| 摘要 |
<p>The use of protected capability registers to hold the physical base and limit addresses and access rights for a block of memory and the way in which such registers are loaded using System Capability Tables and reserved segment pointer tables is well known in the prior art. In the present invention the normal capability load instruction has been enhanced in four major ways: (a) allowing additional capability classes to be handled (b) instituting a "load on use" facility (c) instituting capability propagation control and (d) implementing access reduction facilities The capability classes comprise (i) system store, (ii) system resource, (iii) local store and (iv) passive capability. The "load on use" facility speeds up the load capability instruction and the change process instruction. The propagation control mechanism introduces an access bit which controls the storing of the capability pointer preventing the passing of the pointer from one process to another, whereas the hardware access reduction facility enables a capability to be loaded into a capability register with reduced access right.</p> |
