发明名称 DIGITAL INTEGRAL NETWORK
摘要 PURPOSE:To increase the noise absorbing characteristics without increasing the delay time of the output response, by securing a coincidence between the delay time of response to the change of output caused by the change of input and the maximum time of duration of the noise contained in the input signal and to be absorbed. CONSTITUTION:An integrating operation is given based on a certain rule to the ditital coded input signal 30, and at the same time an arithmetic circuit is added to give the upper and lower extreme values to the result of operation as well as to secure a continunation of the above-mentioned arithmetic operation following the result of the preceding operation. Then the state of output is inverted at 42 according as the passing direction is toward the increment or decrement when the result of operation passes through the threshold level fixed previously. And in case the result passes through the threshold level in the direction of increment, the result of operation applied to the comparator 42 is set identical 38 to the upper extreme value and in case the result passes through the threshold level in direction of decrement, the result is set identical 44 to the lower extreme value, respectively.
申请公布号 JPS56110333(A) 申请公布日期 1981.09.01
申请号 JP19800011968 申请日期 1980.02.05
申请人 FUJITSU LTD;NIPPON TELEGRAPH & TELEPHONE;OKI ELECTRIC IND CO LTD;NIPPON ELECTRIC CO;HITACHI LTD 发明人 OOSAKI TAKAAKI;KIKUCHI SHIROU;TSUTSUMI TAKEHIKO;ASAKURA JIYUNJI;ENAMI SHIROU
分类号 H03K5/1252 主分类号 H03K5/1252
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