| 摘要 |
In a data processing system which predecodes and queues a plurality of instructions for sequential presentation to an execution unit, and which includes a plurality of instruction-addressable general registers which can be utilized for temporary data storage or source of address modifying information, an interlock mechanism is provided to detect when an instruction is being decoded which requires use of a general register for address modification, but which register has not yet received new data by execution of an instruction awaiting execution in the queue of instructions. Two fields are associated with each instruction awaiting execution in the instruction queue. They identify one or more of the general registers to be loaded with data by execution of the instruction. Compare logic associated with each register of the instruction queue detects when the general registers identified by the fields in the queue include the general register to be used as address modification data by the instruction presently being decoded. Decoding and address formulation are prevented when the compare exists for any instruction awaiting execution in the queue.
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