| 摘要 |
PURPOSE:To eliminate the thyristor effect by a parasitic bi-polar transistor and prevent the generation of an overload current by providing each FET with a bias potential generating circuit and connecting them to given regions when a C-MOS.IC is constituted by P and N channel MOS type FETs. CONSTITUTION:In an N type Si substrate 12, a P type well region 20 is formed by diffusion. The portion of the substrate 12 where the region 20 does not exist is used for a region to form a P channel MOS type FET element QP, and a P<+> type source region 14 and a P<+> type drain region 16 are provided here. Between these regions an insulated gate electrode 18 is formed. Moreover, the portion of the substrate 12 including the region 20 is used for a region to form an N channel MOS type FET element QN, and similarly an N<+> type source region, an N<+> type drain region 24 and an insulated gate electrode 26 are formed in the region 20 respectively. In said constitution, moreover, the elements QP and QN are provided with bias potential generating circuits 30A and 30B respectively. The circuit 30A is connected to the substrate 12 and the region 14, while the circuit 30B is connected to the regions 20 and 22. |
