| 摘要 |
PURPOSE:To elevate the adjustment sensitivity by generating a necessary delay by means of combination of the individual delay circuits, and selecting one of them. CONSTITUTION:The delay times generated by the delay circuits 1-4 are denoted as delay times of GX2<0>, GX2<1>, GX(2<2>-1), GX(2<3>-2), respectively, to the basic gate delay time G. And, for instance, the timing signal of the total delay time 3G can be obtained by the delay circuit 3, or combination of the delay circuit 1 and the delay circuit 2. That is to say, by the selecting circuit 9, a selective signal is provided to the gate circuits 5, 6, 8 in order to select the input signals 10, 11, 13, and also a selective signal is provided to the gate circuit 7 in order to select the output signal 16. Also, in the same way, the delay circuit 1 and the delay circuit 2 are combined. And, the same total delay time is generated by combining the separate delay circuit, and a necessary delay is obtained by selecting the combination which has few errors. |
