发明名称 DELAY SYNTHESIZING CIRCUIT
摘要 <p>PURPOSE:To store faithfully the carrier frequency of an input signal, by detecting the phase difference of the joints of pulses of the signals in a delay synthesizing loop and then controlling the degree of phase shift of a phase shifter in the synthesizing loop to eliminate the phase difference. CONSTITUTION:The high frequency signal of the input is amplified by the amplifier 8 via the switch 1 and the signal injection coupler 2 and then distributed to the phase detector 14 and the signal take-out directional coupler 4 by the distributor 9. One of the outputs of the coupler 4 turns into an output signal, and the other output is amplified by the amplifier 11 via the delay line 10 to be distributed to the detector 14 and the delay line 13 by the distributor 12. The output of the line 13 is applied again to the input terminal of the amplifier 8 via the phase shifter 5 and the switch 7. At the same time, the detector 14 received an application of signals from the distributors 9 and 12 produces the signals according to the phase difference of each signal. This phase difference signal is applied to the phase shifter 5 controlling the phase of signal and via the phase shifter driving circuit 15.</p>
申请公布号 JPS56107622(A) 申请公布日期 1981.08.26
申请号 JP19800010443 申请日期 1980.01.31
申请人 BOEICHO GIJUTSU KENKYU HONBUCH;MITSUBISHI ELECTRIC CORP 发明人 HOSONO MUTSUMASA;MATSUDA MUTSUHIRO;SUGIE KIYOKAZU
分类号 G01S7/28;G01S7/32;H03H11/26;H03L7/02;(IPC1-7):03H11/26 主分类号 G01S7/28
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