| 摘要 |
PURPOSE:To enable to completely change the receiving circuit to an integrated circuit, by constituting the system so that binary information, frame information and clock information can be transmitted by means of one transmission circuit. CONSTITUTION:When a binary signal is transmitted, the signal is inverted (for instance, the signal is made to rise) in the specified direction at the start point of the unit width T of a constant period, and corresponding to the contents (''0'', ''1'') of the binary information, the signal is inverted (for instance, the signal is made to brake) in the opposite direction of said direction by shorter width than width of T/2 (for instance, it is made ''0''), or longer width (for instance, it is made ''1''), and it is transmitted. On the other hand, when the frame information F is transmitted, the inversion of signal is halted (the signal is not made to rise or break) as to 1 signal of unit width T, and the information is transmitted. The receiving circuit generates the clock CLI of the same phase as the rise (or breaking) point of the transmission signal, the CLII (T/2 delay phase) and the CLIII (T delay phase), and the binary information, the frame information and the clock information are detected from the CLI and the transmission signal, the negative signal of the CLIII and the logical product of the CLI, and the logical sum of the CLI and III, respectively. |
