发明名称 DECODER
摘要 PURPOSE:To elevate an error correction capacity and also execute a disappearance correction, by detecting a disappearance state of each bit by which each syndrome is formed, and constituting the decoder so that both the error correction and the disappearance correction of a receiving data can be executed by utilizing said result. CONSTITUTION:The OR circuit groups 351-354 read out from the disappearance memory part 300 both the disappearance information bit and the disappearance inspection bit corresponding to the receiving bit which forms each syndrome of prescribed number out of the syndromes generated by the syndrome generation part 210, and detect whether there is a disappearance bit in each syndrome or not, by taking each logical sum. In case when the output code value of each OR circuit is ''1'', the gate circuits 361-364 obstruct the passage of each syndrome corresponding to said value. The number of syndromes in case when the output of the gate circuit is ''1'' is counted by the adder circuit 271, the number of ''1'' which is output from the OR circuit group is counted by the adder circuit 371, and the correction is executed by deciding in accordance with the prescribed expression and outputting the correction bit.
申请公布号 JPS56107659(A) 申请公布日期 1981.08.26
申请号 JP19800011908 申请日期 1980.01.30
申请人 MITSUBISHI ELECTRIC CORP 发明人 SUGIYAMA YASUO
分类号 H03M13/00;H03M13/23;H04L1/00 主分类号 H03M13/00
代理机构 代理人
主权项
地址