发明名称 TEST EVALUATION DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To carry out prearranged cutoff of a power supply and protect an evaluation device as well as shorten test time by providing a first fail stop function which does not perform tests after occurrence of fault in parallel measurement of plural samples. CONSTITUTION:The waveforms of outputs from comparison circuits 10, 10 which compare function test data of two test samples 13, 13 arranged in parallel with a voltage of power supply 2 on an output data level are compared for evaluation with reference waveforms based on a pattern memory 4, a mask memory 6, etc. added to a comparison control circuit 9. When a fault has occurred, a first fail stop signal 18, turning to an inhibit signal, changes an input mode into a drive circuit 8 on the faulty side to an output mode through the intermediary of a first fail stop control circuit 16, logic circuits 17, 17, etc. In turn, the circuit 8 is caused to develop high impedance, resulting in the interruption of required power supply and subsequent discontinuation of tests on the faulty side. While tests on the other side are protected against the effect of the faulty side so that tests may be continued. For this reason, it is possible to shorten test time.
申请公布号 JPS56107174(A) 申请公布日期 1981.08.25
申请号 JP19800010299 申请日期 1980.01.31
申请人 NIPPON ELECTRIC CO 发明人 NAGATOME KENICHI
分类号 G01R31/26;G01R31/28;G01R31/316;H01L21/66 主分类号 G01R31/26
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