发明名称 |
FM data demodulator including circuit for eliminating step distortion |
摘要 |
A circuit arrangement is disclosed for the correction of step distortions in a transmission of data employing frequency-modulated data signals. The circuit arrangement contains a demodulator which compares time durations between edges of the frequency-modulated data signals with a measuring time duration generated in a timing element and generates demodulated data signals after an integration. The demodulated data signals are compared in a comparator to reference signals and the signals at the output of the comparator are integrated in an integration element. The integration element emits control signals to the timing element. With these control signals the measuring time duration is changed in such manner that the step distortions of the demodulated data signals are opposed.
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申请公布号 |
US4286224(A) |
申请公布日期 |
1981.08.25 |
申请号 |
US19790102669 |
申请日期 |
1979.12.12 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
PAETSCH, WERNER |
分类号 |
H04L27/156;(IPC1-7):H03D3/00;H03K9/06;H04L27/14 |
主分类号 |
H04L27/156 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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