发明名称 |
SISTEMA DE PROCESSAMENTO DE DADOS E SINTETIZADOR DE FREQUENCIA |
摘要 |
The central processing unit of a data processing system employs a decoder 40 to decode macroinstructions held in an instruction register 19 under the control of a program counter 20. Each decoded macroinstruction provides a sequence of first microinstructions on an 18-bit bus 39. Each first microinstruction comprises a 4-bit address field applied to a sequencer 33 which also receives bits from the decoder 40 and addresses a ROM 31 which provides the first microinstructions. A 6-bit field of each first microinstruction addresses another ROM 32 which provides one of 64 second microinstructions of 33 bits each, HORM O-32. Fields of the second microinstructions are modified in accordance with two 4-bit modifier fields V1 and V2 from the first microinstruction in a modification circuit 34 which provides 35-bit output microinstructions HCOMT 0-34. These output microinstructions are applied to a decoder 35 whose outputs control the machine states of the CPU. A system bustiming system and a frequency synthesizer are also provided. |
申请公布号 |
BR8100790(A) |
申请公布日期 |
1981.08.25 |
申请号 |
BR19818100790 |
申请日期 |
1981.02.09 |
申请人 |
DATA GENERAL CORP |
发明人 |
MARCH R;BERNSTEIN D;DRUKE M;GUSOWSKI R;CARBERRY R;BUCKLEY E |
分类号 |
G06F9/22;G06F1/04;G06F1/08;G06F7/68;G06F9/26;G06F13/22;G06F13/36;G06F13/362;G06F13/40;G06F13/42;H03K23/66;H03K23/68 |
主分类号 |
G06F9/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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