发明名称 ADDER
摘要 PURPOSE:To obtain the sum of two inputs and the sum of the three inputs that include the two inputs by providing sub-adders which add the lower bits of two inputs and other one input and selection circuits separately to selection type adders of two inputs one output. CONSTITUTION:The respective bytes of the upper places 0-2 of the inputs A, B of bytes 0-3 respectively input to byte adders 24-29, respectively, and the lowermost byte 3 inputs to an adder 30 and a carry save adder CSA32. The input C of a 1 byte width is applied to the CSA32 which in turn outputs the sum S of the three inputs and the carry C and inputs these to a byte adder 31. The circuits 24, 26, 28 add the bytes based on the absence of any carry from the respective lower bytes and the circuits 25, 27, 29 add these based on the prescence of carry from the respective lower bytes, and these circuits output the respective added results to selection circuits 52-57. A prospective carry circuit 45 is inputted with the bytes 0-3 of the inputs A, B and the carry C of the circuits 30, 31, and inputs the carries to the respective upper bytes to the circuits 52-57. The circuits 52-57 select the inputs according to the presence or absence of the carries from the circuit 4 and simultaneously output the sums of the two inputs and the three inputs.
申请公布号 JPS56105540(A) 申请公布日期 1981.08.22
申请号 JP19800006887 申请日期 1980.01.25
申请人 HITACHI LTD 发明人 KUBO KANJI
分类号 G06F7/509;G06F7/50;G06F7/506;G06F7/507;G06F7/508 主分类号 G06F7/509
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