| 摘要 |
<p>PURPOSE:To reduce the size of a memory cell by a method wherein one terminal of a selection transistor is connected to a row-line and the gate of the selection transistor is connected to a column-line and the other terminal of the selection transistor is connected to the series circuit of a plurality of cell transistors whose control gates are connected to the respective column-lines. CONSTITUTION:The output of a data input circuit 25 is supplied to the gate of an N-channel MOS transistor 26. One terminal of the transistor (hereinafter referred to as 'Tr') 26 is connected to a high voltage source Vp and the other terminal of Tr 26 is grounded through the series circuit of a selection Tr ST and cell Tr's CT1-CT4. If, after signals X1 and W1-W4 are at the high voltage level and electrons are injected into the floating gates of Tr's CT1-CT4, the signals W1-W4 are successively set to the zero level and a data D is at the 1 level at that time, Tr 26 is turned on and electrons are emitted from the floating gate of the corresponding cell Tr. When the data is read, the signals R and X1 are set at the 1 level and the control gate of the cell Tr to be read is set at the zero level and the potential of a node N2 is detected.</p> |
