| 摘要 |
PURPOSE:To decrease the occupying area per bit in the semiconductor memory device by reducing the capacity of a digit line and decreasing the area of the occupying area of the digit line with a multilayer wire. CONSTITUTION:A field inversion preventing P<+> type region 12 and an N type region 13 are formed on a P type semiconductor substrate 11. The first polysilicon layer 15 is formed through a thin oxide film 14 on the substrate 11, and the first polysilicon layer 15 is used as the one electrode of a memory cell capacity. The second polysilicon layer 16 is alternately formed through the surface of the substrate 11 and a thick oxide film 17 as a digit line and an address selecting transistor drain. The third polysilicon layer 19 is formed via an oxide film 20 between the first polysilicon layer 15 and the second polysilicon 16 as an address selecting MOSFET gate electrode. Thus, the memory cell having smaller occupying area per bit can be carried out, and the integration of the device can be increased. |
