发明名称 |
PROCESS OF READING A SELECTED CELL IN A CAPACITOR MEMORY ARRAY |
摘要 |
An improved method for reading metal dual insulator semiconductor capacitor memories is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. According to the invention, a small variable voltage is applied across a selected cell or cells. The range of voltage includes a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. The unselected cells are maintained in a depletion state in which their capacitance is a minimum. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell. |
申请公布号 |
GB1595910(A) |
申请公布日期 |
1981.08.19 |
申请号 |
GB19800020037 |
申请日期 |
1977.10.26 |
申请人 |
MASSACHUSETTS INSTITUTE OF TECHNOLOGY |
发明人 |
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分类号 |
G11C11/401;G11C16/04;H01L21/306;H01L21/761;H01L21/764;H01L21/822;H01L23/52;H01L27/10;(IPC1-7):11C7/00;01L27/04;11C11/24 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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