| 摘要 |
PURPOSE:To prevent a malfunction caused by a mixture of noise and other factors, by using the voltage controlling oscillator in a PLL circuit for the clock source of a counting circuit in common. CONSTITUTION:The PLL circuit is composed of the phase comparator 4, LPF5, voltage controlling oscillator 2 and frequency 3. The output of the oscillator 2 is counted by the counting circuit 16 when the terminal Q of the FF12 is at an L level, and the FF12 is inverted when the circuit 16 counts up to the set number. The output of the NAND gate 14 is inhibited by the output of the FF12 during working of the counting circuit. Accordingly no malfunction is caused although the noise mixes at the input terminal 13. |
