| 摘要 |
The time of day clock in data processing apparatus is run off the clock for the apparatus via control logic (16, 18) responsive to both clocks by selecting the processor clock cycle T such that a binary multiple N of the time of day unit cycle D contains an integral number K of processor cycles T or ND = KT in accordance with the equation:… D = (R + @) T,…… where R is the integer nearest the actual D/T ratio, N and represents the number of D cycles containing R processor cycles T while X represents the number of D cycles of longer or shorter duration than R processor cycles needed to establish the actuel proportional relationship between the two cycles over the period ND. |
