| 摘要 |
<p>PURPOSE:To lower a cost by reducing one process related to a mask and to prevent a drop in a yield rate by a method wherein a length of a gate electrode in a depletion transistor is shortened as compared with that of an ordinary enhancement transistor. CONSTITUTION:A source-drain diffusion layer 2 is situated in such a way that it is sandwiched between oxide films 1; gate electrodes 3 are formed in such a way that they cross the source-drain diffusion layer 2. What is different from a conventional setup is that depletion transistors 4 are constituted not by an additional VT controlled ion implantation method but by shortening a length of a gate electrode. A concrete difference of the length of the gate electrode is about 0.3-0.8mum; it is not necessary to control the length so accurately as the length of the gate electrode of an ordinary transistor.</p> |
