发明名称 SPEED CONTROL SYSTEM
摘要 PURPOSE:To control stably even when a load abruptly changes in a speed control using selectively a clutch and a brake by storing an error signal sampling value preceding by one and raising the gain of the engaged clutch when the sampling value is lowered. CONSTITUTION:An actual speed signal 1 is converted into a pulse train via a waveform shaper 5 in the speed control system using selectively the clutch and the brake. A revolution number indicating signal 2 is converted into a clock pulse responsive to the indicated value by a V/F converter 10, the clock pulses 7 responsive to the actual speed signal are counted and are applied to a latch circuit 13. The sampling value preceding by one held in the latch circuit 13 is shifted to the second latch circuit 17. Thus, the sampling values of both the latch circuits 13 and 17 are compared, and any of the clutch signals 3 and 4 is outputted therefrom. In this case, when the sampling value of the circuit 13 is higher than a predetermined value, the clutch signal 3 is produced for longer time.
申请公布号 JPS56101392(A) 申请公布日期 1981.08.13
申请号 JP19800003476 申请日期 1980.01.18
申请人 HITACHI LTD 发明人 TAKADA KAZUAKI
分类号 D05B69/26;D05B69/22;G05D13/00;H02P15/02;H02P29/04 主分类号 D05B69/26
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