| 摘要 |
<p>PURPOSE:To increase the actual working efficiency of system, by connecting a part of main memory unit with auxiliary memory unit with a transmission line different from the memory bus. CONSTITUTION:The central operation and processing unit 13 is connected to a bus controller 17 with an exclusive bus 20, and main memory units 11a-11d are connected to the controller 17 with the memory bus 18. The main memory units 11c, 11d are connected to the auxiliary memory units 15a, 15b via signal lines 16a, 16b by means of input and output devices 14a, 14b. Since the memory bus 18 and the signal lines 16a, 16b are independent buses, the information transmission between the devices 15a, 15b and the units 11c, 11d can be executed in asynchronizing with the information transmission between the device 13 and the units 11c, 11d.</p> |
