发明名称 RESET*COUNTER TEST MODE SWITCHING CIRCUIT OF ELECTRONIC TIMER
摘要 PURPOSE:To shorten the check time of the counter and make the on-delay operation possible, by switching the number of output stages of the counter according to the input voltage. CONSTITUTION:When input voltage VS is 1/3VDD or less, outputs V01 and V02 of gate circuit 7 are L level, and the number of output stages of counter circuit 2 is switched by the input of input terminal R. When input voltage VS is 1/3VDD- 2/3VDD, output V01 of gate circuit 7 becomes H level, and the test mode output is set to connect counters F1 and F1'. When input voltages VS is 2/3VDD or more, output V02 of gate circuit 7 becomes H level to reset all counters. Then, the on-delay operation is possible to changing input voltage VS from the H level to the L level.
申请公布号 JPS56100524(A) 申请公布日期 1981.08.12
申请号 JP19800003842 申请日期 1980.01.17
申请人 MATSUSHITA ELECTRIC WORKS LTD;MATSUSHITA ELECTRIC IND CO LTD 发明人 YODA KENICHI;TOGAWA HIDEO;OGAWA EIZOU;KAYAHARA MASAO
分类号 H03K5/135;H03K17/28;H03K21/40 主分类号 H03K5/135
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