发明名称 MEMORY CONTROL SYSTEM
摘要 <p>PURPOSE:To realize an economical load distribution type multiprocessor system, by making it possible that respective control devices use the program memory provided commonly in time division. CONSTITUTION:Control processing device 11 executes one instruction during the time from the start of the control clock period to, for example, the 3/4 period and outputs the memory address of program memory 200 to address line 31 during the rest 1/4 period. Selector circuit 300 selects address line 31 during the said 1/4 period and inputs address information to memory 200. The instruction output to output line 401 of memory 200 is distributed to device 11 by distributing circuit 400. Device 11 sets this instruction in itself and executes it at the next period. Other control devices 12-14 are operated similarly by control clocks PC2-PC4 whose phase is shifted successively from the phase of control clock PC1 of device 11 by every 1/4 period. As a result, memory 200 is used time-divisionally.</p>
申请公布号 JPS5699559(A) 申请公布日期 1981.08.10
申请号 JP19800000863 申请日期 1980.01.10
申请人 OKI ELECTRIC IND CO LTD;NIPPON TELEGRAPH & TELEPHONE;NIPPON ELECTRIC CO;HITACHI LTD;FUJITSU LTD 发明人 NAKAMURA YUKIO;YAMADA SHIGEKI;YAMAUCHI HIDEO;INUI YOSHIO;FUJITA HIROSHI;KIMURA AKIO
分类号 G06F15/16;G06F12/00;G06F13/16;G06F15/177 主分类号 G06F15/16
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