| 摘要 |
PURPOSE:To enable to transfer data between a buffer and input-output equipment with a variable cycle clock by providing a toggle buffer to the data input-output line if a dynamic memory and by reading and writing data out of and into the buffer through a controller with a clock of a definite cycle same as the refreshing operation. CONSTITUTION:Input data (DATA IN) are sent synchronizing with a data clock or synchronizing clock CLK for requesting data transfer from timing part 2 provided in the system. As buffer 21 comes to full of data, controller 3, while inputting input data to buffer 22, transfers the data of buffer 21 to memory part 1. Under the control of controller 3, memory part 1 writes data of buffers 21 and 22 into a dynamic RAM area or transfers the readout data to buffers 23 and 24. In those toggle buffers 23 and 24, data transferred from memory part 1 are stored under the control of controller 3. Thus, controller 3 controls data transfer between buffers 1-24 and memory part 1 and also controls the refreshing operation of the dynamic RAM area. |
