发明名称 RECEIVING SYSTEM OF DIGITAL SIGNAL
摘要 PURPOSE:To increase the spectrum resolution of a discrete Fourier conversion and then signal enhance the time property of a receiver, by resetting the counter when the input arrives and ends each. CONSTITUTION:The input PCM signal is applied to the multiplier 10 and the power detecting circuit 2. When the input signal more than the prescribed power is detected at the circuit 2, the output is applied to the D-FF3 and 4. The Q outputs of the FF3 and 4 reset the counter 7 for coefficient ROM address via the exclusive OR gate 5 and the inverter 6. As a result, the contents of the coefficient ROM8 is given to the multiplier 10 after the parallel-serial conversion 9 and then multiplied by the input PCM signal to be supplied to the totalizing circuit of discrete Fourier conversion via the terminal 11. Accordingly, an operation is started for the discrete Fourier conversion immediately after the arrival and end of the input signal.
申请公布号 JPS5698050(A) 申请公布日期 1981.08.07
申请号 JP19800000596 申请日期 1980.01.09
申请人 HITACHI LTD;NIPPON TELEGRAPH & TELEPHONE 发明人 MURAMATSU RIYUUJIROU;KIKUCHI SHIROU
分类号 H04L7/00;H04L27/00 主分类号 H04L7/00
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