Digital low-pass filter circuit - has flip=flop set and reset by and-gates and coupled to output delay circuit

摘要

The filter has an RS flip flop (3) with a set input (5) and a reset input (4). The flip flop's output is passed to a delay circuit (9). The input signal to the filter is passed to the set and reset inputs via two gates (7,8). The gates are controlled by the output from the delay circuit such that they are opened alternately. The gates are AND-gates. One AND-gate receives the input signal via an inverter (6). The delay circuit consists of at least one D-flipflop or it may be a series of logic gates or monostable flipflop. An RC timing circuit may define the cut-off frequency. The transition between the pass and stop regions of the filter is as steep as possible.