| 摘要 |
<p>A calculator having semi non-volatile memory capability (data retention) utilizing a CMOS process, a low power microcomputer with on-chip and external data retention capability, and multiple partition power control of circuit groups. Incorporation of a first and second switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the clocked logic and the display interface and keystroke detect circuitry to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal and external RAM, or to selectively connect in combination the first and second switched voltages. In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements. In yet another embodiment, the clocked CMOS logic of the system is forced to a designer predefined output logic level in the inactive power down mode. Thus, semi-non-volatile memory capability, power down standby, and display only capabilities may be achieved.</p> |
