| 摘要 |
PURPOSE:To extend the charge holding time of the MOS memory integrated circuit device by forming a substrate and another conductivity type layer at a part of the outer periphery of a capacitive part for holding the charge, applying a predetermined potential thereto and collecting the minority carrier. CONSTITUTION:A capacity is formed between the electrode 1' connected to the N type layer 1a' of a P type Si substrate 2' and the substrate 2' through an insulating film. The MOS FET is formed of N type layers 5a', 5a' and gate electrode 3'. An N type layer 11 is formed at least on a part of the outer periphery of a charge holder A', and the size, depth, width and density thereof are suitably determined by the voltage applied thereto and the voltage of the IC or the like. When the minority carrier injected to the substrate generated by the peripheral circuit B' is diffused to the layer 11 according to this configuration, it is largely collected to the depletion layer of this layer, and the minority carrier is not almost arrived at the charge holder A'. Therefore, the charge is erased only due to the leakage of the P-N junction 1a', and the holding time can be remarkably improved. |
