发明名称 CONTROLLER FOR MEMORY PATROL
摘要 PURPOSE:To enable to prevent the production of 2-bit error, by supperssing data readout/write-in from the memory immediately after the power supply, reading out the data one by one words after the achievement of a given status, and correcting one bit error for re-write-in. CONSTITUTION:Immediately after the application of power supply, the data readout/write-in from the storage device 16 is suppressed with the control means. Further, the control means is operated after the achievement of a given status, data is read out from the storage device 1 one by one, error correction is made with the error correction circuit 19 if there is one bit error in the data, so that re-write-in can be made to the storage device 16. For example, by using the circuit as shown in Figure, the start timing of memory patrol is made with the T counter 1, and the address signal of the address counter 7 is made to +1 through the output signal of the T counter produced every given time, allowing to make data readout, correction and re-write-in word by word.
申请公布号 JPS5694595(A) 申请公布日期 1981.07.31
申请号 JP19790173183 申请日期 1979.12.28
申请人 FUJITSU LTD 发明人 AOKI TAKASHI
分类号 G06F11/10;G06F1/24;G06F11/22;G06F12/16;G11C29/00 主分类号 G06F11/10
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