发明名称 INSPECTING METHOD FOR PATTERN
摘要 PURPOSE:To perform inspection of the mask pattern of an IC without using a memory group for comparison and a comparison check-up circuit. CONSTITUTION:Scanning systems A and B make scanning reversely to each other from the right and left of the direction X and detection signals are converted to binarized signals (l) and (r) respectively. The signal (r) is inputted in a memory 6 from a lower rank, while the signal (l) being inputted to a memory 7 from an upper rank. Partial scanning corresponds to the length of a chip pattern, while the memories have bit capacities corresponding to this length. At the time of completion of the partial scanning, a signal (e) is given to trigger the generation 16 of a pulse, controlling the shift pulse (s) and the check-up pulse (t) and comparing and checking up the contents A0 and B0 of the memories. After the first comparison, the content A0 of the memory is transferred by one bit to the right, while B0 being transferred by one bit to the left, both by the pulse (s) for checking up again, and these processes are repeated, the results of which are stored by the pulse (t) into a memory 10. Next, the scanning systems A and B are moved at the interval (p) of the pattern for making the check-up in the same way, and when the scanning is completed for the direction of this axis X, it is transferred to a subsequent line. In this way, the inspection of the pattern can be performed without using the memory group for comparison and a check-up circuit therefor.
申请公布号 JPS5694628(A) 申请公布日期 1981.07.31
申请号 JP19790170844 申请日期 1979.12.27
申请人 FUJITSU LTD 发明人 NAKASHIMA MASAHITO;FUJIWARA KATSUMI;HIZUKA TETSUO
分类号 G01N21/88;G01N21/956;G03F7/20;H01L21/027;H01L21/66 主分类号 G01N21/88
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