发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To enable to use either one of the parity inspection mechanism provided at the memory or SEC-DED mechanism, by providing SEC-DED means, and the selective output means of either the output or data output. CONSTITUTION:The parity inspection circuit 3 making parity check for the data transmitted to be stored in the memory, data memory section 2, and one bit error correction - 2-bit error detection (SEC-DED) means 1, are provided. Further, the output from the SEC-DED means 1 and the data output read out from the data memory means 2 are input and either one of them is selectively output to the data switching circuit 5. Further, a selective control signal is fed to the switching circuit 5, then either one of the said inputs can selectively be output.
申请公布号 JPS5694596(A) 申请公布日期 1981.07.31
申请号 JP19790173189 申请日期 1979.12.28
申请人 FUJITSU LTD 发明人 ITOU SHIYUUJI
分类号 G06F12/16;G06F11/10;G11C29/00 主分类号 G06F12/16
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