发明名称 ERROR DETECTING SYSTEM OF CHECKING CIRCUIT
摘要 PURPOSE:To eliminate a redundant memory and then realize a detection for the circuits relating to error detection, by installing a prescribed by-pass circuit to the memory. CONSTITUTION:The device is provided with the gate 14 to give a bypass to the data given from the writing register 6 to the memory 1 and the gate 15 to give a bypass to the code from the Hamming code generating circuit 5 to the memory 1, the inverter 18 which gives the ON/OFF control to the gates 14 and 15. Each gate is turned off in the normal operation mode and then turned on in the error detection diagnosis mode. As a result, the parity bit, the Hamming code and the data are transmitted to the parity checking circuit 8 and the Hamming checking circuit 9 with no intervention of the memory 1.
申请公布号 JPS5693196(A) 申请公布日期 1981.07.28
申请号 JP19790170086 申请日期 1979.12.26
申请人 FUJITSU LTD 发明人 KAMIYANAGI YUTAKA
分类号 G06F11/08;G06F11/10;G06F12/16;G11C29/00 主分类号 G06F11/08
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