发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To increase using efficiency of a memory module, by performing an error check by identifying the addition of a error correcting code or the parity for reading data given from a memory part. CONSTITUTION:The device is provided with the data memory part 2; data writing control part 3; data memory device control part 4; and data correction/output part 6 respectively. The output part 6 checks the presence or absence of the error based on the control signal supplied from the parity identifying part 5 as well as the error correcting code ECC in case the data read out of the part 2 contains the parity, and at the same time delivers the reading data. On the other hand, the presence or absence of the error is checked in case the readout data contains ECC. Then the data is corrected when the 1-bit error exists to be delivered, and the presence of the 2-bit error is detected in the case of the 2-bit error.
申请公布号 JPS5693195(A) 申请公布日期 1981.07.28
申请号 JP19790170082 申请日期 1979.12.26
申请人 FUJITSU LTD 发明人 KAMIMOTO SHIGEMI;TATE NOBUYOSHI;TASAI MATSUAKI
分类号 G06F12/16;G06F11/10;G11C29/00 主分类号 G06F12/16
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