| 摘要 |
PURPOSE:To obtain a high-speed static MOS memory IC having a small amount of consumption, by cutting the power supply to the memory in the wait mode and at the same time supplying the electric power only to the block of the divided address decoder groups in the action mode. CONSTITUTION:The prescribed bit part of the address signal supplied from the address inverter group 40 is turned into the selection signal to select the logic circuits 50-53 within the logic circuit group 300. Then the blocks 42-45 divided into the X decoder group 400 corresponding to the circuits 50-53 in the action mode of the memory by the AND process between the outputs of the circuits 50-53 plus the chip enable signal sent from the chip enable circuit 41 are selected. Furthermore the memory corresponding to the address given from the group 40 in the selected blocks is selected. As a result, the power supply is cut off in the nonaction and wait modes, and at the same time the power is supplied only to the selected address decoder block even in the action mode. Thus the useless power consumption can be avoided. |
