| 摘要 |
PURPOSE:To prevent erroneous search operation, by setting the holding time of a holding circuit equal to the lock time of PLL. CONSTITUTION:Latch circuit 92 sets the value of frequency dividing ratio N from controller 12 as a time-division signal. For this purpose, counter 120 is divided into parts 120-1, 120-2 and 120-3, which are synchronized with timing signals T1, T2 and T3 by AND gates 121-1, 121-2 and 121-3 to send the frequency dividing ratio N value of counter 120 to a frequency divider. Frequency divider 9 performs sampling by AND gates 94-1, 94-2 and 94-3 with timing signals T1.t, T2.t and T3.t and stores frequency dividing ratio N in latch circuits 92-1, 92-2 and 92-3 divided corresponding to counter 120. Although the value of ratio N of latch circuit 92 has a discontinuous part generated during a search, the discontinuous part is detected by detecting circuit 122 and holding circuit 123 and until the output of holding circuit 123 is ceased, frequency conversion triggering and search stop detection are invalidated. |
