| 摘要 |
PURPOSE:To ensure the omission of mask process when low density impurities are formed to secure voltage resistance by providing a low density impurity region between a source and drain wire electrode on one hand and a gate electrode on the other. CONSTITUTION:The source layer 6 of an N<+> type Si layer, the source wiring electrode 11 of Al, the drain layer 7 of N<+> type Si layer, the drain layer of an N<+> type Si layer, the drain wiring electrode 12 of Al, a gate SiO2 film 10 and the gate electrode 13 of Al are provided in an FET forming region partitioned by a field SiO2 film 2 on the surface of a P type Si substrate and P<+> type channel cutting layer 3 formed thereunder. An N<-> type Si layer 5 is formed by P ion injection via a thin gate SiO2 film with self-coordination made using the electrodes and a thick SiO2 film 10 as mask. |
