| 摘要 |
<p>PURPOSE:To prevent the cracking during the dicing process from expanding to the integrated circuits for preventing the dicing process from producing any defective chips by a method wherein a groove is formed on an interlayer line of dicing in a dicing region. CONSTITUTION:Multiple integrated circuits formed on a semiconductor wafer 5 are diced to split them into individual chips. During this dicing process, a dicing cutter 6 can be prevented from side slipping at the initiation of the dicing process by a groove 3. Furthermore, the integrated circuits can be prevented from cracking until the dicing cutter 6 reaches the bottom of the groove 3 while the cutting operation is started as soon as the cutter 6 reaches the bottom of the groove 3. During the cutting operation, the dynamic stress is imposed on the dicing region 2 to start cracking. However, the depth of the groove 3 can be moderately adjusted to make the cracking have no effect on the integrated circuits so that the dicing process may not produce any defective chips at all.</p> |
