| 摘要 |
<p>The microprocessor system comprises a combination logic circuit which is provided with five inputs and two outputs. At least one selected output address bus line of the microprocessor is connected to the first input of the combination logic circuit the memory read control output thereof is connected to the second input of the combination logic circuit and the read control input of the memory, the peripheral device read control output thereof is connected to the fourth input of the combination logic circuit and the peripheral device write control output thereof is connected to the fifth input of the combination logic circuit. The first output of the combination logic circuit is connected to the write control input of the peripheral device. The combination logic circuit is constructed so that when the first input thereof is in logic "true" state, the logic slate of the first output thereof is identical with the logic OR-relation of the logic states of the second and fourth inputs thereof, the logic state of the second output is identical with the logic OR-relation of the logic states of the third and fifth inputs; when the first output thereof is in logic "false" state, the logic state of the first output is identical with the logic state of the fourth input and the logic state of the second output is identical with the logic state of the fifth input. </p> |
