| 摘要 |
<p>The direct access semiconductor memory has a matrix of memory cells, eeach employing a data storage capacitor. the capacitor of each cell in each column is connected to a corresponding column line, in response to a voltage on the row address conductor, with a detection amplifier for each column line. The memory has a number of address inputs connected to a row address register and an address decoder for actuating the address conductor of the specified row. the memory also has a signal input for column address signals, connected to a column address register, a data line and a column decordeR, for activating the detection amplifier of the addressed column. The memory data input is connected to an input register for data awaiting transfer to the memory cells and an output register, connected to a data output to which the data can be transferred from the memory cells, with a clock generator controlling the data transfer and the addressing of the memory cells.</p> |
