| 摘要 |
In data processing systems with memory units of different memory cycle time, there is a problem of synchronous interaction between the processor (P) and the memory units (ASP, VSP) selected by it. In order to be able to ensure this synchronous interaction, the operating speed of the processor (P) must be adapted to the operating speed of the memory unit (ASP, VSP) in each case selected. The present method indicates an approach which provides for such adaptation with little expenditure. This is achieved in that, when a memory unit is selected by the processor (P) the supply of the clock pulses (TG) applied to the processor is blocked by the write or read command (W or, respectively, R) appearing in each case within a write or read cycle, with interposition of a suppression element (UG), and is only enabled again when the relevant memory unit outputs a return message (T) indicating the end of the write or read process. The method can be used in programme-controlled telecommunication switching systems. <IMAGE>
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