| 摘要 |
<p>PURPOSE:To prevent malfunction by correcting the phase of a bit signal for demodulation by detecting a prescribed number of continuous intervals of transition points of a demodulated signal while a timing pulse that corresponds to a width of two bits is fixedly in phase with a bit pulse signal for demodulation. CONSTITUTION:Clock signal C is applied as a clock input to 4-bit binary counter 20 and ripple carry output H of 4-bit counter 8 is connected to enable terminal EN. Further, AND gate 21 receiving two kinds of output H of counter 8 and Q' output L of D (Delay)-EF7 and OR gate 22 receiving two kinds of gate output M and ripple carry output I of counter 20 are provided and the outputof the gate 22 is applied to preset load terminal LD of counter 20. Then, output I of counter 20 is applied to preset terminal PR of D-FE7 to correct the phase of bit clock pulse J for demodulation. In the figure, D-FFs are represented as 2, 3 and 5, and an exclusive OR gate as 4.</p> |
