| 摘要 |
PURPOSE:To enable a high speed processing, by reading out the data form the memory section asynchronizingly with the operation to the transit to the memory section through the sampling of serial bit signal. CONSTITUTION:The serial bit signal L is sampled at the clock signal CL0 at the reception SA and set to the shift register SR0. Next, the data in the register SR0 is transferred to the memory section M. The data stored in the memory section M is read out with another low speed clock CL1 from the clock CL0 and set to the shift registers SR1, SR2. The content of the registers SR1, SR2 is moved to the chacter assembly CHC. Thus, since the assembling of the characters can be exceuted in a low speed, the bit reception of high speed line can be made. |
