BIT ERROR DETECTING CIRCUIT FOR USE IN A DIGITAL SIGNAL TRANSMISSION LINE

摘要

A bit error detecting circuit for detecting errors in digital signal transmissions is disclosed. An input digital signal is fed to a clock recovery circuit which reproduces a clock signal to clock first and second decision circuits and a digital pattern generator. The input digital signal is fed to the first decision circuit which produces a decision output based on a first reference level. The input digital signal is also added to a predetermined binary code pattern produced by the pattern generator and the combined signal is fed to the second decision circuit which produces a decision output based on a second reference level. The two decision outputs are fed to respective inputs of an Exclusive-OR circuit. The use of the pattern generating circuit contributes to very stable operation which can be further improved by incorporating a capacitor in the circuitry for adding the input signal and the predetermined signal.