发明名称 HORIZONTAL SYNCHRONIZING SIGNAL SEPARATING CIRCUIT
摘要 PURPOSE:To easily make the circuit an IC, by raising the noise resistance, characteristic, reducing the characteristic required for the peripheral circuit, and also removing a capacitor from the circuit. CONSTITUTION:When a composite synchronizing signal is provided to the input terminal 301, logical ''0'' is output by rise of an input signal to the output terminal 306 of the FF309, and the counter 303 is made a count state. The counter 303 counts a clock pulse provided to the counter terminal 308, and when the count number has attained to a fixed value, the C terminal output is made logical ''1''. The time requirEd for making this count number attain to the fixed value is decided in advance so as to become 0.5-1H. As soon as the C terminal output becomes logical ''1'', the terminal 306 becomes logical ''1'', and the counter 303 is reset. As a result, a coincidence pulse of rise of a horizontal synchronizing signal, and phase is obtained by the output terminal 305 of the FF309. According to such a constitution, even if a noise has entered when the potential of the terminal 307 is low, it is masked by the outputs of the FF309 and the counter 303, and it does not exercise influence on the output waveform.
申请公布号 JPS5685980(A) 申请公布日期 1981.07.13
申请号 JP19790162274 申请日期 1979.12.14
申请人 SUWA SEIKOSHA KK 发明人 IKEDA KATSUYUKI;NAKAZAWA YOSHIO
分类号 H04N5/10;(IPC1-7):04N5/10 主分类号 H04N5/10
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