| 摘要 |
PURPOSE:To make it possible to easily make the formation of IC, by cascading a gate circuit, also providing a gate circuit for taking the AND condition of an input signal and a delay signal, and constituting the circuit. CONSTITUTION:The prescribed delay time is obtained by cascading the gate circuits G1-G5, and also the gate circuit G4, G5 by which the AND condition of the input signal (a) provided to the input terminal IN and the delay signal can be obtained are provided on the stage in the course of the cascade connection, and the final stage, and the input signal (a) is provided to them. Accordingly, if the input signal (a) rises in the process where the input signal (a) is delayed in turn, it is reset immediately, and the delay signal is not output. In this way, the circuit is constituted of the gate circuit only, it is possible to make formation of IC easy. |
