| 摘要 |
PURPOSE:To make it possible to easily integrate the circuit, by setting and resetting the FF by the respective even-and odd-ordered AND output signals of optional numbers of plural inverting circuits which have been cascaded. CONSTITUTION:The even output signals c, e, g, i, k of optional number of the inverting circuits N1-N16 whose delay time is equal are input to the NAND circuit 1, and the odd-ordered output signals b, d, f, h, j of optional numbers are input to the NAND circuit 2. The respective signals m, l of the circuits 1, 2 are made set and reset signals of the FF which is composed of the NAND circuits 3, 4, and the circuits 1-4 have an equal delay time. According to this constitution, a signal having pulse width which is larger than the delay time by the circuits N1-N16 is output as an output signal (n), as it is from the circuit 3 after said delay time, a signal having smaller pulse width than said signal is not output, and therefore, the pulse width can be discriminated. Since this circuit is constituted of a gate circuit, it is possible to integrate it. |
