| 摘要 |
PURPOSE:To obtain an FET having high operation speed and low power consumption with a plurality of main electrodes by partly removing the electrode regions, forming recesses thereon, and eliminating unnecessary capacity increase. CONSTITUTION:An N<-> type layer 13 becoming channel region 13 and base region 13a is epitaxially grown on an N<+> type Si substrate 12 becoming source region, and N<+> type drain region, P<+> type gate region 14 and P<+> type emitter region 15 are diffused therein. In this configuration a recess portion V2 is particularly formed at the center of the drain region, is divided into regions 11a and 11b, and recess portions V3 and V4 are respectively formed also on the peripheries of the regions 14 and 15. Subsequently, the whole surface is covered with an insulating film 7, a window is opened thereat, divided drain electrodes 1a, 1b are covered on the regions 11a, 11b respectively. Gate emitter and source electrodes 4, 5 and 2 are respectively covered on the regions 14, 15 and on the back surface of the substrate 12. |
