| 摘要 |
PURPOSE:To perform digital frequency modulation by controlling a frequency step- down ratio by inputting a binary-coded modulated signal to a binary counter that steps-down the frequency of highly stable clock pulses. CONSTITUTION:In the fall of clock pulse A, JK flip-flops 1-5 and 12 operate. When the binary counter consisting of JK flip-flop 1-5 counts up to a prescribed count value of 16, output B rises up to [1] and output C of NAND gate 11 falls down to [0]. As a result, flip-flops 1-5 and 12 are reset and output C is held at [1] again. In this state, the registration gate consisting of NAND gates 13 and AND gates 14 and 15 are opened and binary-coded modulated signals B0, B1 and B2 are set in JK flip-flops 1, 2 and 3. Consequently, carrier signal B obtained by frequency step-down is frequency-modulated by the binary-coded modulated signal. |
