发明名称 |
Data processing apparatus adapted for memory readback checking. |
摘要 |
<p>To provide for a more economic buffer capacity through facilitating high speed readback check of data transferred to a cyclic memory (16) from a free input buffer before the source data is lost, the cyclic memory is organized into a number of data blocks, each interleaved with or simultaneously accessible with the other data blocks. Thus, a long data record comprises several data blocks and therefore several cycles of the memory. A readback check of data transferred is accomplished by writing data into one check number generator (51) and one data block in a first cycle, writing data into another block on the second cycle while reading back the first data block to a second check number generator (52), continuing in this manner until the entire record is transferred, and reading the last block of written data into the check number generator (52). The two generated check numbers are then compared to detect any error and effect a retransfer if required before the source of the record is lost by overwriting. </p> |
申请公布号 |
EP0031499(A2) |
申请公布日期 |
1981.07.08 |
申请号 |
EP19800107633 |
申请日期 |
1980.12.04 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BREWER, JAMES ARTHUR;LOWY, JOHN ALFRED |
分类号 |
G06F3/06;G06F11/10;G06F11/14;(IPC1-7):06F11/10;11B5/09;06F11/16 |
主分类号 |
G06F3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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