| 摘要 |
<p>PURPOSE:To absorb jitter and to prevent malfunction, by performing delay correction to the frame in a loop transmission system and avoiding the missing of trailing of the preceding frame, when the synchronizing word enters the synchronizer and is again output. CONSTITUTION:A frame 4a taking the synchronizing word SYN as the head is fed to a synchronizer 1, it is converted into a parallel data at a serial/parallel conversion register SP, the synchronizing word SYN is detected at the synchronizing circuit FSYN, the partial frame number corresponding to partial frames D1-Dn is produced, and split instruction is given to a frame split circuit BUF. The partial frames D1-Dn and the frame number are written in the pushup memory FLFO, and the partial frames D1-Dn are stored in the frame memory FMEM as the unit word. Further, the partial frames D1-Dn are sequentially read out according to the sequence of write-in from the memory FMEM at the address counter CTOUT, they are converted into parallel data at a parallel serial conversion register PS, and they are transmitted to the transmission line by taking the synchronizing word SYM as the trailing.</p> |
