| 摘要 |
Disclosed is a non-sequential counter. The non-sequential counter comprises, in a preferred embodiment, six inverters coupled together as a three stage shift counter, the input of which is generated according to a feedback term provided by the outputs of each one of the inverter stages. Counters having more than three stages are also disclosed. The feedback term is provided by disclosed decoder circuitry. The non-sequential counter counts through all possible states; thus, a counter having N stages will count non-sequentially through 2N possible binary states.
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